Ch 1 · 15 Hardware and Virtual Machines · AS & A Level Computer Science 9618
Topic 1 of 3 in Hardware, System Software and Security — AS & A Level Computer Science 9618 — 90 lessons.
Introduction
This lesson goes deeper into processor design: RISC and CISC processors and pipelining, parallel architectures, and virtual machines. It then extends logic circuits to adders and flip-flops, and shows how to simplify logic with Boolean algebra and Karnaugh maps. (Syllabus topic 15: sections 15.1–15.2.)
Key ideas — 15.1 (a) RISC and CISC
🧑🏫 Teacher's explanation
Imagine you are running a kitchen. A CISC processor is like a professional chef with a massive cookbook containing complex recipes like "Make a Beef Wellington." One single command triggers a long sequence of many small actions (chopping, searing, pastry work). Because the instructions are so complex and vary in length, it is hard to predict exactly how long each task takes, making it difficult to multitask efficiently.
📖 Definitions
🔍 Worked example — Easy
Identify whether the following instruction characteristics belong to RISC or CISC:
🔍 Worked example — Standard
A CISC processor executes a single instruction that performs: Load from memory arrow Add to register arrow Store to memory. A RISC processor must achieve the same result using only LOAD, STORE, and ADD instructions. Write the RISC sequence.
🔍 Worked example — Exam-style
Compare the interrupt handling approach. If an interrupt occurs during a complex, multi-cycle CISC instruction versus a single-cycle RISC instruction, which is generally easier to manage and why?
⚠️ Common errors
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🎯 Exam question
(a) Compare the instruction sets of RISC and CISC processors. [4] (b) Explain why the use of pipelining is more efficient in a RISC processor than in a CISC processor. [3] [7 marks]
Key ideas — 15.1 (b) Pipelining and registers in RISC
Pipelining is instruction-level parallelism: the stages of different instructions overlap, like a production line. With a five-stage pipeline (fetch, decode, execute, memory access, write back), once the pipeline is full, one instruction finishes every clock cycle.
🧑🏫 Teacher's explanation
Imagine a busy sandwich shop. If one person takes the order, then makes the sandwich, then wraps it, then serves it, the shop is slow because the person is doing everything one by one. This is non-pipelined processing. Now, imagine a production line: one person takes the order, the next person toasts the bread, the next adds fillings, and the next wraps it. Even though a single sandwich takes 4 minutes to make, a new sandwich is finished every minute because everyone is working simultaneously on different stages of different sandwiches. This is pipelining.
📖 Definitions
🔍 Worked example — Easy
A RISC processor uses a 4-stage pipeline: Fetch (F), Decode (D), Execute (E), and Write-back (W). If the processor starts executing 4 instructions (I1, I2, I3, I4) at clock cycle 1, how many clock cycles will it take for I4 to complete its Write-back stage?
🔍 Worked example — Standard
In a RISC processor, the instruction cycle is divided into 5 stages. If the processor is running at a clock frequency of 2 ext GHz, what is the theoretical maximum number of instructions that can be completed per second once the pipeline is full?
🔍 Worked example — Exam-style
A CISC processor takes 10 cycles to complete a complex instruction. A RISC processor uses pipelining and completes one instruction every 1 cycle. If both processors execute 100 instructions, calculate the ratio of time taken by the CISC processor to the RISC processor (assuming no pipeline stalls).
⚠️ Common errors
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🎯 Exam question
(a) Explain why having instructions of different lengths would negatively affect the efficiency of the pipeline. [2] (b) Describe how the use of a large number of registers supports the performance of a RISC processor. [2] [4 marks]
Key ideas — 15.1 (c) Interrupt handling
🧑🏫 Teacher's explanation
Imagine you are reading a book. A CISC processor is like a person reading a very long, complex sentence; if someone taps you on the shoulder (an interrupt), you finish the entire sentence before responding. A RISC processor is like someone reading a series of short, quick sentences using a conveyor belt (the pipeline). If someone taps you on the shoulder while you are halfway through a sentence, you have a dilemma: do you finish that specific sentence, or do you quickly clear your mind and deal with the interruption immediately?
📖 Definitions
🔍 Worked example — Easy
A CISC processor is executing a complex instruction that requires 5 clock cycles. An interrupt signal arrives at cycle 2. When will the processor check the interrupt and start the ISR?
🔍 Worked example — Standard
A RISC processor has a 4-stage pipeline (Fetch, Decode, Execute, Write-back). An interrupt occurs while instruction i is in the 'Execute' stage. If the processor chooses to 'flush' the pipeline, what happens to instructions i+1 and i+2?
🔍 Worked example — Exam-style
A processor must save its state during an interrupt. List the three essential pieces of information that must be stored in the stack/registers to allow the processor to resume execution.
⚠️ Common errors
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🎯 Exam question
(a) Explain why the processor must save the contents of the registers before executing the Interrupt Service Routine (ISR). [2] (b) Describe one method the processor can use to handle the instructions currently in the pipeline when an interrupt occurs. [2] [4 marks]
Key ideas — 15.1 (d) Computer architectures (Flynn's classification)
Massively parallel computers contain a very large number of processors (thousands or more), each with its own memory, linked by a fast network. They work together on one problem that can be divided into many parts that run at the same time (e.g. weather forecasting, simulating molecules). Characteristics: each processor works on part of the task; they communicate by passing messages; the software must be written for parallel execution; very high processing speed.
🧑🏫 Teacher's explanation
Imagine you are running a busy restaurant kitchen. Flynn's Taxonomy is simply a way to classify how many chefs (processors) are working and whether they are following the same recipe (instructions) or working on different ingredients (data).\n\nIf you have one chef making one burger at a time, that is SISD. If you have one chef telling ten assistants to all chop onions simultaneously, that is SIMD. If you have ten chefs all working on different parts of a massive banquet independently, that is MIMD. MISD is like having two different chefs look at the same steak to ensure it is cooked perfectly—one checks the temperature, the other checks the color—but they are both looking at the same single piece of meat.\n\nWhen we scale this up to 'Massively Parallel Computers', we aren't just talking about a kitchen with four chefs; we are talking about a factory with thousands of specialists, all communicating via headsets to solve one giant problem, like predicting the weather.
📖 Definitions
🔍 Worked example — Easy
Identify the Flynn's Taxonomy classification for a standard single-core CPU from the 1980s that processes one instruction at a time on one piece of data.
🔍 Worked example — Standard
A GPU (Graphics Processing Unit) is performing a brightness adjustment on an image. It applies the same 'multiply by 1.2' instruction to 1,000,000 different pixel values simultaneously. Which architecture is this?
🔍 Worked example — Exam-style
A supercomputer is used for weather forecasting. It consists of 5,000 processors. Each processor is assigned a different geographic region (e.g., North Atlantic, Sahara Desert) and runs different mathematical models (e.g., pressure, humidity, wind speed) on the data specific to that region. Classify this architecture and state one characteristic of the hardware used.
⚠️ Common errors
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🎯 Exam question
Key ideas — 15.1 (e) Virtual machines
A virtual machine (VM) is software that emulates a computer system. A host computer runs a hypervisor (or emulation software), which lets one or more guest operating systems run as if each had its own hardware.
🧑🏫 Teacher's explanation
Imagine you own a large house (the physical hardware). Instead of living in one room, you decide to build several miniature, self-contained apartments inside that house. Each apartment has its own front door, its own kitchen, and its own rules. Even though they all share the same foundation and plumbing (the host's CPU and RAM), the people in Apartment A don't know what the people in Apartment B are doing. This is exactly what a Virtual Machine (VM) does. It is a software-based 'computer' that acts like it has its own dedicated hardware.
📖 Definitions
🔍 Worked example — Easy
Identify the role of a Virtual Machine in a cloud computing environment where 50 different customers use the same physical server.
🔍 Worked example — Standard
A developer wants to test a new application designed for macOS on their current Windows 11 laptop. Explain why a Virtual Machine is a suitable solution and identify one limitation.
🔍 Worked example — Exam-style
Compare the performance of a native application (running directly on hardware) versus an application running inside a Virtual Machine.
⚠️ Common errors
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🎯 Exam question
(a) Define the term 'Virtual Machine'. [2] (b) State one advantage and one disadvantage of using a Virtual Machine for this purpose. [2] [4 marks]
Key ideas — 15.2 (a) Half adders and full adders
A half adder adds two bits, giving a sum (S) and a carry (C).
🧑🏫 Teacher's explanation
Imagine you are adding numbers by hand on a piece of paper. When you add 7 + 5, you write down '2' and 'carry over' a '1' to the next column. Digital hardware does exactly this, but it only understands two states: 0 and 1.
📖 Definitions
🔍 Worked example — Easy
Complete the truth table for a half adder with inputs A and B. Determine the Boolean expressions for Sum (S) and Carry (C).
🔍 Worked example — Standard
A full adder has inputs A=1, B=1, C_in=0. Calculate the Sum (S) and Carry-out (C_out).
🔍 Worked example — Exam-style
Using the full adder logic, calculate the result of adding two 2-bit binary numbers: 11_2 + 01_2.
⚠️ Common errors
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🎯 Exam question
(a) Draw a truth table for a full adder with inputs A, B, and C_in, and outputs S and C_out. [4] (b) State the Boolean expression for the Sum (S) output. [1] [5 marks]
Key ideas — 15.2 (b) Flip-flops
A flip-flop is a circuit with two stable states that stores one bit. Its output depends on its inputs and its previous state (feedback from the outputs to the inputs). Flip-flops are the basic data storage elements used in registers and static RAM (SRAM).
🧑🏫 Teacher's explanation
Imagine a light switch that doesn't just turn on or off, but actually 'remembers' which position it was in even if you stop touching it. In digital electronics, a flip-flop is that memory. It is a circuit that uses 'feedback'—meaning the output is wired back into the input—to create a stable state.
📖 Definitions
🔍 Worked example — Easy
Complete the truth table for an SR flip-flop. If the current state is Q=1, barQ=0 and the inputs are changed to S=0, R=1, what is the new state?
🔍 Worked example — Standard
A JK flip-flop is currently in state Q=0. A clock pulse occurs when J=1 and K=1. What is the new state of Q?
🔍 Worked example — Exam-style
A system uses an SR flip-flop to store a single bit. If the input sequence is S=1, R=0 followed by S=1, R=1, what is the final state of Q and why is this state problematic?
⚠️ Common errors
🧠 Quick check 1
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🎯 Exam question
(a) Complete the truth table for the JK flip-flop, showing the output Q for all possible combinations of J and K. [3] (b) Explain why the JK flip-flop is preferred over the SR flip-flop in high-speed synchronous circuits. [2] [5 marks]
Key ideas — 15.2 (c) Boolean algebra
Notation: A.B means A AND B; A + B means A OR B; Ā means NOT A.
🧑🏫 Teacher's explanation
Boolean algebra is the mathematical language of digital logic. In a computer, everything boils down to high and low voltages (1 and 0). Instead of using numbers like 5 or 10, we use variables that can only be True (1) or False (0). Logic gates like AND, OR, and NOT act as the operators that manipulate these values.
📖 Definitions
🔍 Worked example — Easy
Simplify the expression: A · B + A · overlineB
🔍 Worked example — Standard
Simplify the expression: overlineoverlineA + B using De Morgan's Laws
🔍 Worked example — Exam-style
Simplify the expression: A + overlineA · B
⚠️ Common errors
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🎯 Exam question
Key ideas — 15.2 (d) Karnaugh maps
A Karnaugh map (K-map) is a grid of the outputs of a truth table, arranged so that adjacent cells differ by only one variable (Gray code order: 00, 01, 11, 10). Groups of adjacent 1s show which variables can be eliminated.
Worked example
NOT (A.B + C) = NOT (A.B) . C̄ (De Morgan on the OR) = (Ā + B̄).C̄ (De Morgan on the AND).
🔍 Worked example — Easy
Simplify the expression overlineA · B using De Morgan's Laws.
🔍 Worked example — Standard
Simplify the expression overlineA + B + C using De Morgan's Laws.
🔍 Worked example — Exam-style
Show that overline(A + B) · C = (overlineA · overlineB) + overlineC using De Morgan's Laws.
⚠️ Common errors
Common mistakes
Practice
Answers: (1) Any three: RISC has fewer, simpler instructions; fixed-length instructions; one cycle per instruction; only load/store access memory; more registers; hard-wired control; easier to pipeline. (2) Instructions are the same length and take one cycle per stage, so the fetch, decode and execute stages of different instructions can overlap, and one instruction completes every cycle once the pipeline is full. (3) (a) SIMD; (b) MIMD. (4) Benefits, any two: several OSs on one machine; isolation of guests; legacy software; easy backup/migration. Limitation: e.g. slower than real hardware / needs a powerful host. (5) S = 0, C = 1. A full adder also has a carry-in input, so it adds three bits. (6) S = R = 1 gives an invalid state where Q and Q̄ are both 0; in a JK flip-flop J = K = 1 toggles the output, and the clock synchronises changes. (7) A.Ā + A.B = 0 + A.B = A.B. (8) All four 1s have B = 1 (columns 10 and 11 in both rows): the result is B.